Advance the future of AI/ML hardware acceleration by shaping cutting-edge TPU technology. This role offers the chance to drive innovation in custom silicon solutions powering Google's AI/ML applications and services. You will leverage your expertise in design and verification to ensure the reliability of complex digital designs, focusing on TPU architecture and its integration within AI/ML-driven systems.

Join a team dedicated to redefining AI and Infrastructure. Empower Google customers with breakthrough capabilities and insights through unparalleled scale, efficiency, reliability, and velocity. Contribute to groundbreaking innovations, deliver computing power to global services, and provide platforms for developers to build the future.

Take ownership of the entire verification lifecycle, from planning and test execution to coverage closure. Meet stringent AI/ML performance and accuracy goals by building robust constrained-random verification environments. Effectively expose corner-case bugs and guarantee the reliability of AI/ML workloads on hardware. Collaborate closely with design and verification engineers on active projects, ensuring functionally correct design blocks.

Key responsibilities include planning digital design block verification, identifying critical verification scenarios with design engineers, and defining coverage measures for stimulus and corner-cases. Debugging tests alongside design engineers to ensure design integrity and measuring progress towards tape-out are crucial. Develop a constrained-random verification environment using SystemVerilog and UVM.

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, coupled with 8 years of experience in RTL-level digital logic verification is essential. Proficiency in SystemVerilog or Specman/E for FPGAs or ASICs is required. Demonstrated experience in verifying digital systems, including IP/subsystem/SoC verification within the networking domain (e.g., packet processing, bandwidth management, congestion control), and verification of standard IP components/interconnects like microprocessor cores and memory subsystems is necessary.

Preferred qualifications include a Master's degree or PhD in a related engineering or computer science field, with a focus on computer architecture. Experience with industry-standard simulators, revision control, and regression systems is beneficial. Familiarity with AI/ML Accelerators or vector processing units, and a comprehensive understanding of the full verification life cycle are highly regarded. Exceptional problem-solving and communication abilities are key.