Join a forward-thinking team dedicated to developing cutting-edge custom silicon solutions that drive Google's direct-to-consumer products. You will be instrumental in creating innovative hardware that delights millions globally. Your expertise will define the next era of hardware experiences, focusing on exceptional performance, efficiency, and seamless integration.

Our mission at Google is to make information universally accessible and useful. We achieve this by merging Google's strengths in AI, Software, and Hardware to engineer radically helpful experiences. Our team pioneers new technologies and hardware, aiming to make computing faster, more fluid, and more potent, ultimately enhancing people's lives through technology.

Develop comprehensive verification plans for complex digital design blocks at the subsystem level, thoroughly understanding design specifications and collaborating with design engineers to pinpoint critical verification scenarios.

Construct and refine constrained-random verification environments utilizing SystemVerilog and Universal Verification Methodology (UVM). Alternatively, perform formal verification using SystemVerilog Assertions (SVA) and leading industry formal tools.

Define and implement all necessary coverage measures for stimulus and corner cases to ensure thorough validation.

Collaborate closely with design engineers to debug tests and ensure the delivery of functionally accurate design blocks.

Achieve coverage goals to identify verification gaps and confirm progress towards tape-out readiness.

A Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, coupled with equivalent practical experience, is required.

Possess a minimum of 8 years of hands-on experience with verification methodologies and languages, including UVM and SystemVerilog.

Demonstrated experience in building and maintaining robust verification test benches, test cases, and comprehensive test environments.

Experience with advanced concepts such as low power design, debug, Gate-Level Simulation (GLS), and formal verification is highly desirable.