Join a forward-thinking team dedicated to crafting custom silicon solutions that will power Google's next-generation direct-to-consumer products. This role offers the chance to innovate on hardware that delights millions globally, shaping the future of computing with exceptional performance, efficiency, and integration.

We are a collective of Google AI, Software, and Hardware experts focused on developing pioneering technologies. Our mission is to enhance computing speed, fluidity, and power, ultimately improving lives through advanced technology.

Drive the verification strategy for complex digital design blocks at the subsystem level by thoroughly understanding design specifications and collaborating with design engineers to pinpoint critical verification scenarios.

Develop and refine robust constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM), or conduct formal verification using SystemVerilog Assertions (SVA) and leading formal tools.

Define and implement comprehensive coverage measures for stimulus and corner-cases.

Collaborate with design engineers to debug tests and ensure the functional correctness of design blocks.

Achieve coverage closure to identify verification gaps and demonstrate readiness for tape-out.

A Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, coupled with equivalent practical experience, is required.

We seek candidates with a minimum of 8 years of experience in verification methodologies and languages like UVM and SystemVerilog.

Proven experience in developing and maintaining verification test benches, test cases, and environments is essential.

An advanced degree (Master's) in Electrical Engineering, Computer Science, or equivalent practical experience, along with expertise in low power, debug, Gate-Level Simulation (GLS), and formal verification, is highly desirable.