Join a pioneering team dedicated to developing cutting-edge custom silicon solutions that will define the future of Google's direct-to-consumer products. You will play a crucial role in innovating hardware experiences that millions of users will love. Your expertise will be instrumental in shaping next-generation hardware, delivering exceptional performance, efficiency, and seamless integration.

This position offers the opportunity to impact products loved by millions globally. We are building advanced hardware for radical new user experiences, combining Google's strengths in AI, Software, and Hardware to make computing faster, more powerful, and seamlessly integrated into daily life.

Take ownership of the complete verification lifecycle, from planning and test execution to ensuring coverage closure. A key focus will be on meeting rigorous performance and accuracy targets for AI/ML workloads on Tensor Processing Unit (TPU) hardware. You will develop advanced constrained-random verification environments designed to uncover complex corner-case bugs and guarantee the robustness of AI/ML computations.

Responsibilities include: - Defining comprehensive verification strategies and detailed test plans for full chip, subsystem, and block levels. - Architecting scalable SystemVerilog and UVM verification environments featuring constrained-random stimulus generation, protocol checkers, and automated scoreboards. - Providing technical leadership to global verification teams, conducting thorough reviews of test plans and verification code. - Collaborating closely with architecture and RTL design teams to resolve ambiguities, address corner-case bugs, and refine specifications. - Establishing bit-accurate reference models using C/C++ via DPI-C for dynamic verification of intricate pixel-processing algorithms and video pipelines.

We are seeking a seasoned Senior Design Verification Engineer with a strong foundation in hardware verification. A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a closely related field, or equivalent practical experience, is essential.

Key qualifications include: - A minimum of 10 years of experience in hardware verification languages, design verification methodologies, and chip design flows. - Proven experience with high-density micro-display technologies. - Demonstrated experience in developing and managing UVM testbenches.

Preferred qualifications enhance your candidacy: - A Master's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience. - Expertise in ultra-low latency, high-density micro-display technologies such as MicroLED or Micro-OLED for AR/VR XR systems. - Experience in transitioning UVM testbenches to hardware emulation platforms like Palladium or Zebu. - Familiarity with scripting languages such as Python, Perl, and Makefile for efficient automated regression management.