Join Google Cloud and help shape the future of AI/ML hardware acceleration. This role offers the chance to drive cutting-edge TPU technology, powering Google's most demanding AI/ML applications. You will be part of a boundary-pushing team developing custom silicon solutions for Google's TPU, contributing to innovations behind products used by millions.

Leverage your design and verification expertise to validate complex digital designs, with a focus on TPU architecture and its integration within AI/ML-driven systems. The AI and Infrastructure team is redefining possibilities, empowering Google customers with breakthrough capabilities and insights through AI and Infrastructure at unparalleled scale, efficiency, and reliability.

Be at the forefront of Google's groundbreaking innovations, from AI models to global services and developer platforms. Our teams shape world-leading hyperscale computing, working on TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, and systems research.

Own the complete verification life cycle, from planning and test execution to coverage closure, ensuring stringent AI/ML performance and accuracy goals are met. Develop constrained-random verification environments to identify corner-case bugs and guarantee the reliability of AI/ML workloads on TPU hardware.

Collaborate closely with design and verification engineers on active projects, performing detailed verification. Plan the verification of digital design blocks and engage with design engineers to pinpoint critical verification scenarios. Identify and implement all types of coverage measures for stimulus and corner-cases.

Debug tests effectively with design engineers to deliver functionally correct design blocks. Utilize metrics to identify verification gaps and track progress toward tape-out. Create constrained-random verification environments utilizing SystemVerilog and the Universal Verification Methodology (UVM).

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience is required. A minimum of 8 years of experience in verification is necessary, focusing on digital logic at the RTL level using SystemVerilog or Specman/E for FPGAs or ASICs.

Experience in verifying and debugging IPs, subsystems, or SoCs within the Networking domain, such as packet processing, bandwidth management, and congestion control, is highly desired. Familiarity with verifying digital systems using standard IP components and interconnects, including microprocessor cores and hierarchical memory subsystems, is also a plus.

Preferred qualifications include a Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with a specialization in computer architecture. Experience with industry-standard simulators, revision control systems, and regression systems is beneficial. Proficiency in AI/ML accelerators or vector processing units, alongside experience with the full verification life cycle, excellent problem-solving, and communication skills are also valued.