Join Google Cloud as a Senior Design Verification Engineer and shape the future of AI/ML hardware acceleration. This role offers the chance to drive cutting-edge TPU technology powering Google's most demanding AI/ML applications. You will be part of a team pushing boundaries to develop custom silicon solutions for Google's TPUs, contributing to innovations behind products used by millions worldwide.

Leverage your design and verification expertise to validate complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. You will own the entire verification life cycle, from planning and test execution to coverage closure, ensuring stringent AI/ML performance and accuracy goals are met. Build advanced constrained-random verification environments to uncover corner-case bugs and guarantee the reliability of AI/ML workloads on TPU hardware.

Collaborate closely with design and verification engineers on active projects. The AI and Infrastructure team is redefining possibilities, empowering customers with breakthrough AI and Infrastructure capabilities at unparalleled scale, efficiency, and reliability. Our contributions enable groundbreaking AI models, deliver immense computing power to global services, and provide the essential platforms for developers.

Plan the verification of digital design blocks and collaborate with design engineers to pinpoint critical verification scenarios.

Identify and implement all necessary coverage measures for stimulus and corner-cases.

Debug tests effectively alongside design engineers to deliver functionally sound design blocks.

Measure progress and identify verification gaps to demonstrate advancement towards tape-out.

Develop a constrained-random verification environment utilizing SystemVerilog and Universal Verification Methodology (UVM).

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience is required.

Possess a minimum of 8 years of experience in Verification, focusing on digital logic at the RTL level. Proficiency in SystemVerilog or Specman/E for Field Programmable Gate Arrays (FPGAs) or ASICs is essential.

Demonstrate experience in verification and debug of IP/subsystem/SoCs within the Networking domain, including areas like packet processing, bandwidth management, and congestion control.

Experience verifying digital systems using standard IP components and interconnects, such as microprocessor cores and hierarchical memory subsystems, is also necessary.