Join Google Cloud as a Senior Design Verification Engineer and help shape the future of AI/ML hardware acceleration. You will drive cutting-edge TPU technology powering Google's most demanding AI/ML applications. Be part of a team developing custom silicon solutions and verifying complex digital designs, with a focus on TPU architecture within AI/ML-driven systems.

The AI and Infrastructure team is redefining possibilities by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability, and velocity. Our innovations empower Google's groundbreaking AI models, provide global services with computing power, and enable developers to build the future.

This role offers a unique opportunity to contribute to world-leading hyperscale computing, including TPUs, Vertex AI for Google Cloud, and global networking.

Own the entire verification life-cycle, from planning and test execution to coverage closure, ensuring stringent AI/ML performance and accuracy goals are met. Build constrained-random verification environments capable of uncovering corner-case bugs and guaranteeing the reliability of AI/ML workloads on TPU hardware.

Collaborate closely with design and verification engineers on active projects. Plan verification of digital design blocks, identifying critical verification scenarios. Develop comprehensive coverage measures for stimuli and corner-cases. Debug tests effectively with design engineers to deliver functionally correct design blocks, and monitor progress towards tape-out.

Create advanced constrained-random verification environments utilizing SystemVerilog and UVM. Interact with design engineers to pinpoint crucial verification scenarios. Measure verification progress and identify any gaps.

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, alongside equivalent practical experience, is required. You should have at least 8 years of experience in RTL level verification using SystemVerilog or Specman/E for FPGAs or ASICs.

Experience in the verification and debug of IP/subsystem/SoCs within the networking domain, covering areas like packet processing, bandwidth management, and congestion control, is highly desirable. Additionally, experience verifying digital systems with standard IP components and interconnects, such as microprocessor cores and hierarchical memory subsystems, is expected.

Preferred qualifications include a Master's degree or PhD in a relevant engineering or computer science field with a focus on computer architecture. Proficiency with industry-standard simulators, revision control, and regression systems is beneficial. Experience with AI/ML Accelerators, vector processing units, and the complete verification life cycle, alongside excellent problem-solving and communication skills, will further strengthen your candidacy.