Shape the future of AI/ML hardware acceleration by driving cutting-edge TPU technology that powers Google's most demanding applications. Join a team pushing boundaries in custom silicon solutions for Google's TPU.

Contribute to innovations behind beloved products, leveraging design and verification expertise. Focus on verifying complex digital designs, particularly TPU architecture and its integration within AI/ML-driven systems.

The AI and Infrastructure team redefines possibilities, empowering Google customers with breakthrough capabilities and insights. We deliver AI and Infrastructure at unparalleled scale, efficiency, reliability, and velocity for Googlers, Google Cloud customers, and billions of users worldwide. We are the driving force behind Google's groundbreaking innovations, enabling cutting-edge AI models, delivering computing power to global services, and providing platforms for developers to build the future.

Own the full verification life-cycle from planning and test execution to coverage closure, with an emphasis on meeting stringent AI/ML performance and accuracy goals.

Build constrained-random verification environments capable of exposing corner-case bugs and ensuring the reliability of AI/ML workloads on TPU hardware. Collaborate closely with design and verification engineers on active projects.

Plan verification of digital design blocks, interacting with design engineers to identify crucial verification scenarios. Identify and write all types of coverage measures for stimulus and corner-cases. Debug tests with design engineers to deliver functionally correct design blocks and measure progress towards tape-out. Create a constrained-random verification environment using SystemVerilog and UVM.

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience, is required.

Minimum of 8 years of experience in Verification, with expertise in RTL level verification of digital logic using SystemVerilog or Specman/E for FPGAs or ASICs.

Demonstrated experience in verification and debug of IP/subsystem/SoCs within the Networking domain, including areas like packet processing, bandwidth management, and congestion control is desired. Experience verifying digital systems with standard IP components/interconnects such as microprocessor cores and hierarchical memory subsystems is essential.

Preferred qualifications include a Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with a focus on computer architecture. Experience with industry-standard simulators, revision control systems, and regression systems is beneficial. Familiarity with AI/ML Accelerators or vector processing units, and a comprehensive understanding of the full verification life cycle, are highly valued. Excellent problem-solving and communication skills are expected.