Join NVIDIA, a leader in next-generation solutions, as a Senior Custom SOC/IP Verification Engineer. This role is instrumental in crafting life-changing custom SOCs for cutting-edge product lines, from consumer graphics to artificial intelligence and autonomous vehicles.

Become part of a global team dedicated to pushing the boundaries of innovation and shaping the future of computing. This is an opportunity to make a significant impact within a dynamic, technology-driven environment.

Lead comprehensive ASIC design verification efforts for various SOC processing blocks, encompassing planning, execution, coverage closure, and methodology development.

Foster strong collaboration with cross-functional teams, including Architecture, SW/FW, Design, Modeling, Emulation, and Post-Silicon Validation, to ensure robust verification strategies.

Provide essential support to engineering teams in delivering purpose-built ASIC solutions and partner with IP development teams for IP selection and integration.

Analyze SOC and IP architectures, devise detailed verification plans, and establish key performance metrics. Engage in co-development with partners throughout the development, debug, and bring-up phases.

Develop and execute test plans, achieve complete coverage, and establish customer TB infrastructure. Validate critical use cases for power-on and boot sequences.

A proven background in design verification tools such as Synopsys VCS, Cadence Xcelium Simulator, Verdi, JasperGold, and VC Formal is essential.

Demonstrate a consistent history of first-pass success in ASIC development. A Bachelor's or Master's degree in Computer Engineering or Electrical Engineering, coupled with over 5 years of experience in ASIC, IP, or SoC design verification, is required.

Expertise in mixed-language UVM and C++ testbenches, interpreting functional specifications, and constructing thorough test plans is crucial.

Proficiency in developing tools and infrastructure using Perl or Python, alongside a strong understanding of AMBA protocols (AXI, ACE, CHI, ATB), is expected.

Hands-on experience with subsystems incorporating ARM CPUs, LPDDR, HBM, GPUs, DLA, PCIe, and Network on Chip, including performance verification, is highly valued.