Join NVIDIA, a leader in technological innovation, and contribute to groundbreaking processor design in deep submicron technologies. You will be part of a dynamic, multi-functional team dedicated to silicon characterization and its correlation with pre-silicon performance and power models. This role offers the opportunity to shape the future of computing by amplifying human imagination and intelligence.

Generate ATPG patterns for silicon speed path debug, and conduct RTL and gate-level verification for ATPG and non-ATPG patterns. Correlate diagnosis results to identify real design failures, determining root causes and feeding these learnings into pre-silicon design sign-off parameters. You will also focus on RAM correlation, examining circuit failure mechanisms and their limits on silicon, and improving RAM testing methodologies across various types, chips, and processes.

Develop advanced methodologies using DFT infrastructure to analyze mis-correlation components within logic and around RAM. This position is key to enhancing the correlation between silicon behavior and predictive models, driving continuous improvement in our design processes.

A Bachelor of Science in Electrical or Electronics Engineering (BSEE) is required, with a Master of Science (MS) preferred, coupled with a minimum of 8 years of relevant experience. Prior leadership experience is a significant advantage.

Essential skills include a strong understanding of Design-for-Test (DFT) principles and logic design, encompassing scan, BIST, on-chip scan compression, fault models, ATPG, and fault simulation. Experience with RTL/gate-level simulation, testcase development, and debugging is also crucial.

Familiarity with VLSI simulation tools like VCS, pattern generation tools such as Tessent, and proficiency in scripting languages like Python, Perl, Tcl, and Make are expected. Basic knowledge of circuits and RAM functionality/architecture, along with prior experience in Static Timing Analysis (STA) and circuit concepts, will be beneficial. Experience with Post-Silicon data gathering is considered a plus.