Senior ASIC Design Engineer - XBAR IP

NVIDIA

5+ yrs Bengaluru Full Time Hybrid (office + remote)
NVIDIA logo
Posted : today
Actively hiring

Job description

Join NVIDIA's Graphics team as a Senior ASIC Design Engineer, contributing to state-of-the-art memory subsystem components for industry-leading Graphics Processors. This role offers a unique opportunity to influence products across consumer graphics, autonomous vehicles, and artificial intelligence. Become part of a global team pushing technological boundaries and shaping the future of computing.

In this pivotal position, you will be responsible for architectural trade-offs, micro-architecture development, RTL implementation, and delivering fully verified, synthesis/timing clean designs. Collaboration with architects, fellow designers, verification teams, and backend specialists will be key to achieving project goals.

Responsibilities

Take ownership of micro-architecture and RTL development for design modules.

Architect features to meet stringent performance, power, and area requirements.

Collaborate closely with hardware architects to define critical features.

Partner with verification teams to ensure the accuracy of implemented features.

Work with timing, VLSI, and physical design teams to guarantee design meets timing and interface specifications, and is routable.

Engage with FPGA and software teams for design prototyping and software testing.

Contribute to post-silicon verification and debugging efforts.

Qualifications

A Bachelor's or Master's degree, or equivalent experience, is required.

Demonstrated expertise in RTL design for complex units across at least two or three projects is essential.

Proficiency with design and verification tools, such as VCS or equivalent simulation tools, and debug tools like Debussy and GDB, is necessary.

Possess a deep understanding of the complete ASIC design flow, encompassing RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up, and lab debugging.

Expertise in Verilog is a must.

Experience in memory subsystem or network interconnect IP design is a significant advantage.

Strong debugging and problem-solving skills are highly valued.

Familiarity with scripting languages like Python, Perl, or shell scripting is beneficial.

Prior leadership experience guiding small teams of 2-3 members is a plus.

Excellent interpersonal skills and a proactive, team-oriented approach are expected.

Essential Skills

VerilogASIC Design FlowRTL DesignVerificationLogic SynthesisPrototypingDFTTiming AnalysisFloor-planningECOBring-upLab Debug

Good to Have

Memory Subsystem IP DesignNetwork Interconnect IP DesignPythonPerlShell ScriptingTeam Leadership

Highlights

  • Actively hiring

More Details

RoleSenior ASIC Design Engineer - XBAR IP
DepartmentEngineering, ASIC Design
Employment TypeFull Time, Hybrid (office + remote)

About the Company

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