Shape the future of AI/ML hardware acceleration by driving cutting-edge TPU technology. This role offers an opportunity to develop custom silicon solutions that power Google's most demanding AI/ML applications and contribute to innovations used by millions worldwide. You will leverage your design and verification expertise for complex digital designs, focusing on TPU architecture and its integration within AI/ML-driven systems.

The AI and Infrastructure team is redefining possibilities, empowering customers with breakthrough capabilities and insights. We deliver AI and Infrastructure at unparalleled scale, efficiency, and reliability, serving Googlers, Google Cloud customers, and billions of users globally. Our team is the driving force behind Google's groundbreaking innovations, enabling the development of advanced AI models and providing essential platforms for developers.

Develop comprehensive architecture specifications aligned with current and future AI/ML roadmap requirements. Create architectural and microarchitectural power/performance models, along with microarchitectures, to conduct thorough quantitative and qualitative performance and power analysis.

Own the microarchitecture for compute blocks and subsystems, fostering collaboration with hardware design, software, compiler, and ML model teams for effective hardware/software co-design. Establish high-performance hardware/software interfaces.

Evaluate diverse silicon solutions for Google’s data center AI accelerator roadmap, including components, vendor co-developments, custom designs, and chiplets. Drive power, performance, and area improvements for owned modules and contribute to simulation tool development.

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience, is required.

Possess 8 years of experience in architecture and micro-architecture design, with specialization in areas like graphics, Machine Learning, Ethernet/ROCE/UAL/NVlink scale-up/out fabrics, low precision/mixed precision numerics, vector processors, DSP processors, or networking ASICs.

Demonstrated experience with memory hierarchy on chip fabrics, memory controllers, High Bandwidth Memory (HBM), and Dynamic Random-Access Memory (DRAM) technologies is essential.