Join a leading team in architecting and integrating cutting-edge high-speed connectivity IPs and chiplet interconnect solutions. This role focuses on defining critical subsystem architectures, driving protocol compliance, and ensuring seamless integration for advanced semiconductor designs. You will play a pivotal role in shaping the future of interconnect technologies and collaborating with customer architects.

This is an opportunity to work within a collaborative environment that fosters innovation and professional growth. Continuous learning and development are encouraged to enhance both technical and domain expertise, allowing you to contribute significantly to groundbreaking projects.

Lead the architectural vision, integration strategy, and verification planning for high-speed connectivity IPs and chiplet interconnects. Define the architecture for PCIe/CXL/UCIe subsystems and champion the protocol compliance strategy.

Review and refine integration architectures and performance specifications. Develop comprehensive plans for interoperability and compliance testing. Provide expert guidance to verification and validation teams, and liaise directly with customer architects. Support the product roadmap and the adoption of future industry standards.

A minimum of 12 to 20 years of experience in protocol and IP development is essential. Deep expertise in PCIe Gen4/5/6 is a core requirement, alongside proven UCIe architecture knowledge and experience within the chiplet ecosystem.

Strong understanding of protocol stacks and the Link Training and Status State Machine (LTSSM) is crucial. Experience with root complex, endpoint, and switch architectures, as well as integrating PCIe into large System-on-Chip (SoC) designs, is expected. A robust architecture and verification background, coupled with knowledge of SerDes architecture, is also necessary.

Familiarity with CXL protocol, HBM integration, protocol compliance testing, and system-level performance modeling are considered advantageous.