Join the Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) team, powering Microsoft's intelligent cloud mission. SCHIE delivers foundational technologies for over 200 online businesses, including Azure, Office 365, and Xbox Live. We are seeking passionate, high-energy engineers to drive innovation in our expanding cloud infrastructure.

The Data Processing Unit (DPU) team creates high-performance ASICs for efficient data stream handling. Our integrated design approach empowers teams with increased agility and superior performance over traditional CPU-based solutions.

This role focuses on full-chip integration, requiring expertise in C4/package interfaces, chip finishing, and RDL & power delivery. You will lead full-chip integration from early design exploration to signoff, collaborating across teams to define and drive power & signal planning, RDL optimization, and packaging interfaces for cutting-edge silicon projects.

Lead full-chip and package integration, taking ownership from planning to execution. Participate actively in early-phase design planning, including die size, floorplanning, C4/microbump development, and RDL optimization.

Develop and enhance full-chip integration methodologies, collaborating with vendors and partners to align workflows with industry best practices. Address tool-related issues and boost the reliability and efficiency of chip finishing and integration.

Define and drive integration milestones across all project phases, ensuring seamless interaction with the package team and vendors. Manage multiple power domains and islands, guaranteeing design correctness and robustness. Ensure a convergent integration process and drive package closure through final signoff for tapeout. Identify and resolve power delivery and integration issues, providing guidance for floorplan adjustments.

A Bachelor's degree in Computer Engineering, Electrical Engineering, or a related field is required. Candidates should possess over 7 years of physical design experience with a strong emphasis on C4 integration and chip finishing.

Proficiency with ASIC design tools such as DC, ICC2/Fusion-Compiler, and PrimeTime is essential, as is experience with Physical Verification tools like Calibre.

Preferred qualifications include 10+ years of hands-on physical design experience, deep expertise in power planning, C4/microbump deployment, and chip/package interfaces. Skills in flow automation, scripting (TCL/Perl), and tool debug are highly valued. Experience developing and maintaining package signoff checklists and demonstrated tapeout success in TSMC 5nm process or below are significant advantages.