Join Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) as a Principal Silicon Engineer, contributing to the foundational technologies powering Microsoft's global cloud infrastructure. Our team is responsible for the server, data center infrastructure, security, and manageability solutions for over 200 online businesses, including Azure, Office 365, and Xbox Live.

We are developing a highly programmable and high-performance Data Processing Unit (DPU) ASIC, integrating state-of-the-art software and hardware expertise. This innovative solution enhances agility and delivers superior performance over traditional CPU-based alternatives.

This role focuses on Static Timing Analysis (STA) within our DPU silicon team. You will drive STA execution from early design exploration through to final signoff, collaborating across teams to define, develop, and implement the necessary design flows for successful STA execution. Be part of shaping some of the most exciting silicon projects at Microsoft.

Take full ownership of our Static Timing Analysis (STA) execution, ensuring its success from start to finish.

Enhance and update STA methodologies, partnering with vendors to align our flows with industry best practices, resolve tool issues, and boost the overall reliability of STA processes.

Play a key role in early-phase design planning, focusing on STA execution, including full-chip repeater planning, timing budgeting, constraint development, and initial analysis.

Define and manage STA milestones across project phases, overseeing STA rollups, analysis, reporting, ECO generation, and providing guidance to block development teams.

Ensure a convergent STA process and drive STA closure through all design stages, culminating in final signoff for tapeout.

Collaborate with cross-functional teams to pinpoint and resolve boundary timing issues and full-chip STA bottlenecks, offering expert guidance on floorplan adjustments and addressing timing constraints.

A Bachelor's degree in Computer Engineering, Electrical Engineering, or a related technical field is required.

Possess at least 7 years of experience in physical design and Static Timing Analysis (STA).

Demonstrate proficiency with Synopsys design tools, including DC, ICC2/Fusion-Compiler, and PrimeTime.

Preferred qualifications include over 10 years of hands-on physical design experience with a strong emphasis on STA execution and signoff.

Exhibit deep expertise in STA, timing constraints, ECO generation, and STA signoff procedures.

Proficiency in flow automation, scripting languages such as TCL and Perl, and tool debugging is highly valued.

Ability to develop and maintain timing closure checklists, meticulously track and report STA progress, and successfully execute STA closure on schedule is essential.

Proven tapeout experience in TSMC 5nm process technology or below is advantageous.