Join Microsoft's Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) team, the driving force behind our intelligent cloud mission. We are responsible for the core infrastructure powering over 200 Microsoft online businesses, including Azure, Office 365, and Xbox Live. Our Compute Silicon & Manufacturing Engineering (CSME) organization designs and develops cutting-edge computer chips like the Azure Cobalt, delivering strategic advantages to Microsoft and our customers.

As our cloud business expands, timely, high-volume, high-quality, and cost-effective deployment of new hardware infrastructure is crucial. The Verification & Validation team plays a vital role in defining operational success for hardware manufacturing, enhancing planning, quality, delivery, scale, and sustainability for Microsoft's cloud hardware. We seek experienced engineers passionate about customer-focused solutions and industry insights to shape and optimize future cloud infrastructure.

We are actively recruiting a Principal Formal Design Verification Engineer to contribute to our mission and foster our culture. This pivotal role will significantly impact the organization by leading the strategy and execution of formal verification for complex IP and SoC designs.

Take ownership or lead formal verification efforts for Fabric Interconnect architectures, IPs, subsystems, and reusable Fabric components, from initial planning through final signoff. Collaborate closely with architecture, design, and verification teams to establish robust formal verification strategies, methodologies, comprehensive test plans, and clear signoff criteria.

Develop and improve formal verification environments, assertions, abstraction models, checkers, and reusable verification collateral. Drive convergence and ensure timely execution to closure of verification tasks. Conduct in-depth root-cause analysis and resolve complex design and verification issues using formal analysis, simulation, and debugging techniques.

Enhance verification productivity through automation, advanced methodologies, and AI-assisted solutions. Mentor and guide engineers in formal verification best practices, debug techniques, and core methodologies. Uphold Microsoft's core values, including Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity & Inclusion.

A minimum of 12 years of relevant technical engineering experience is required. Candidates must possess at least a Bachelor's or Master's degree in Electrical, Electronics, Computer Engineering, Computer Science, or a closely related field. A minimum of 5 years of hands-on experience in pre-silicon formal verification at the IP, subsystem, or SoC level is essential.

Demonstrated expertise in applying formal verification methodologies to intricate IPs, subsystems, SoCs, or reusable library components is highly desirable. Deep technical knowledge in areas such as Fabric Interconnects, coherency, CHI, AMBA, PCIe, CXL, protocol bridges, virtualization, security, or memory subsystems is preferred. Experience managing verification cycles from planning to signoff across multiple product generations is valuable.

Proficiency in developing scalable formal verification environments, assertions, assumptions, checkers, and reusable verification collateral is beneficial. Experience resolving complex cross-team technical challenges and driving verification closure is a plus. Familiarity with simulation-based verification methodologies, including System Verilog, UVM, assertions, and coverage-driven verification, is important. Strong scripting skills in Python or similar languages for automation and productivity are necessary. Prior experience applying AI-assisted tools to engineering and verification workflows is advantageous.