Join Capgemini Engineering and empower your career within a collaborative global community. We unlock the value of technology to drive scalable, sustainable growth.

This role focuses on owning physical implementation solutions, defining methodologies, and strategizing PPA for complex SoCs. You will act as the technical authority for physical design architecture and feasibility, guiding teams and ensuring project success.

We foster a culture of flexibility, offering remote work options and adaptable schedules for a healthy work-life balance. Our inclusive environment encourages growth, innovation, and excellence, with opportunities for continuous learning in emerging technologies like cloud and AI.

Define and refine physical implementation methodologies for large-scale chips. Develop effective floorplanning and partitioning strategies at the SoC level. Lead the PPA (Power, Performance, Area) closure approach from specification to GDS-II. Conduct early feasibility studies and Quality of Results (QoR) assessments. Establish robust clocking, power, and congestion management strategies. Provide technical guidance and support to global implementation teams. Review signoff readiness and identify potential implementation risks. Support customer technical engagements and provide accurate project estimations.

A minimum of 12 years of experience in Physical Design is required. Demonstrated success with multiple tape-outs in advanced technology nodes (10nm and below). Possess deep expertise in floorplanning, CTS, timing closure, and power optimization. Strong working knowledge of Synopsys ICC2/Fusion Compiler and/or Cadence Innovus. Experience with UPF and designing multi-voltage systems. Proven ability to handle large SoCs with over 100 million gates. Solid understanding of signoff methodologies is essential. Must have TSMC technology node experience and familiarity with AI-based EDA tools (e.g., DSO, Cerberus).