Join a pioneering team dedicated to developing cutting-edge custom silicon solutions that will power Google's future direct-to-consumer products. You will play a crucial role in innovating products used by millions globally, shaping the next generation of hardware experiences with exceptional performance, efficiency, and integration.

This role is integral to the GPU Implementation team, focusing on optimizing Power, Performance, and Area (PPA) for complex logic blocks within the Tensor SOC. Collaboration with RTL, DFT, and Foundation IP teams is key to enhancing PPA and deploying AI workflows to boost productivity and reduce time to market.

Spearhead the end-to-end ASIC RTL2GDS implementation for Graphics Processing Units (GPUs) within the Tensor SOC.

Oversee block and full-chip physical implementation, ensuring high Quality of Results (QoR) in terms of power, timing, and area.

Achieve signoff convergence through comprehensive Static Timing Analysis (STA), Physical Design Verification (PDV), and analysis of IR drop and Electro-Migration (EM).

Drive optimization efforts for power, performance, and area to meet demanding performance targets and cost efficiencies.

Accelerate time to market and improve PPA by integrating Artificial Intelligence (AI) physical design tools and workflows.

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline, alongside equivalent practical experience, is required.

Demonstrated expertise with a minimum of 4 years in physical design, including a track record of two or more successful chip tape-outs.

Preferred qualifications include a Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with a specialization in computer architecture. Experience in optimizing power, performance, and area, particularly for high-performance designs like CPUs, GPUs, or DSPs, is highly advantageous.