Join a pioneering team at the forefront of custom silicon development, powering the next generation of Google's direct-to-consumer products. Contribute to innovations that reach millions worldwide and shape future hardware experiences with exceptional performance, efficiency, and integration.

This role is integral to the GPU Implementation team, focusing on the physical design and layout of complex logic blocks. The objective is to meticulously optimize Power, Performance, and Area (PPA) while collaborating closely with RTL, DFT, and Foundation IP teams. Embracing AI workflows will be key to enhancing productivity and accelerating time-to-market.

Take ownership of the complete ASIC RTL2GDS implementation cycle for Graphics Processing Units (GPUs) within the Tensor SOC. Manage block-level and full-chip physical implementation, ensuring top-tier Quality of Results (QoR) across power, timing, and area.

Drive signoff convergence, encompassing Static Timing Analysis (STA), Physical Design Verification (PDV), and robust IR/EM analysis. Achieve optimal power, performance, and area through targeted optimizations, aiming to enhance both performance and cost-effectiveness. Accelerate time-to-market and elevate PPA by integrating advanced AI physical design tools and workflows.

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline is required, alongside equivalent practical experience. A minimum of 4 years of hands-on experience in physical design, with at least two successful chip tape outs, is essential.

Additionally, a Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with a specialization in computer architecture, is highly preferred. Experience in optimizing power, performance, and area, particularly within high-performance compute domains like CPUs, GPUs, or DSPs, is a significant advantage.