Join a pioneering team crafting custom silicon solutions that drive Google's direct-to-consumer products. You will be instrumental in developing innovative hardware experiences, delivering exceptional performance, efficiency, and integration for products used by millions globally. This role is key to shaping the future of hardware, contributing to cutting-edge designs.

The Platforms and Devices team is dedicated to advancing Google's computing software platforms and first-party devices. We focus on seamlessly integrating Google's AI, software, and hardware to create faster, more intuitive user interactions worldwide, building innovative experiences.

Take ownership of block or subsystem implementation for complex logic blocks, with a strong focus on optimizing power, performance, and area (PPA). Collaborate closely with RTL, DFT, and Foundation IP teams to enhance PPA.

Implement AI workflows to boost productivity, reduce time-to-market, and further improve PPA. You will be responsible for all aspects of ASIC RTL2GDS implementation for the Tensor SOC's central processing unit (CPU).

Ensure signoff convergence, including static timing analysis (STA), physical design verification (PDV), IR drop, and electro-migration (EM). Manage block and subsystem level physical implementation and quality of results (QoR).

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience is required. A minimum of 4 years of professional experience in physical design is essential.

Preferred qualifications include a Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with a specialization in computer architecture. Experience with high-performance designs such as CPUs or GPUs is highly desirable. Familiarity with advanced power optimization techniques and participation in at least three chip tape-outs are also preferred.