Join an innovative team focused on developing cutting-edge custom silicon solutions that power Google's direct-to-consumer products. You will play a crucial role in shaping the future of hardware, contributing to products used by millions globally.

Our mission at Google is to make information universally accessible and useful. This team merges Google's expertise in AI, Software, and Hardware to create truly impactful experiences. We are dedicated to researching, designing, and developing advanced technologies that enhance computing speed, seamlessness, and power, ultimately aiming to improve people's lives through technology.

Take ownership of all aspects of ASIC RTL2GDS implementation for designs demanding high Power, Performance, and Area (PPA).

Effectively manage physical implementation and Quality of Results (QoR) at both block and full-chip levels, focusing on power, timing, and area optimization.

A Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience, is required.

Minimum of 8 years of experience in physical design engineering is essential.

Demonstrated experience in managing high-performance design schemas, specifically with CPUs or GPUs, is necessary.

Preferred qualifications include a Master's degree in Electrical Engineering or Computer Science, or equivalent practical experience, along with expertise in power optimization techniques.