Join a pioneering team developing custom silicon solutions for Google's direct-to-consumer products. You will be instrumental in shaping next-generation hardware, delivering exceptional performance, efficiency, and integration.

Our team merges Google's AI, Software, and Hardware expertise to create innovative computing technologies. We aim to enhance people's lives through advanced technology, making computing faster, seamless, and more powerful.

Spearhead all facets of ASIC RTL2GDS implementation for designs prioritizing Power, Performance, and Area (PPA).

Oversee physical implementation and Quality of Results (QoR), including power, timing, and area, at both block and full-chip levels.

Possess a Bachelor's degree in Electrical Engineering or Computer Science, or demonstrate equivalent practical experience.

Bring 8 years of specialized experience in physical design engineering.

Have a proven track record managing high-performance design schemas for CPU or GPU architectures.

Experience with advanced power optimization techniques is highly preferred.