Join a forward-thinking team dedicated to creating custom silicon solutions that drive Google's consumer products. Your contributions will be vital to the innovation behind products enjoyed by millions globally. You will play a key role in shaping next-generation hardware, delivering exceptional performance, efficiency, and integration.

Oversee all aspects of ASIC RTL2GDS implementation for high Power, Performance, and Area (PPA) designs. You will manage block and full-chip physical implementation, focusing on Quality of Results (QoR) across power, timing, and area.

A Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience, is required. We are looking for at least 8 years of experience in physical design engineering, with a proven track record in managing high-performance design schemas involving CPU or GPU architecture.