Join NVIDIA as a Senior Verification Engineer and contribute to the cutting-edge design and implementation of next-generation PCI Express controllers for world-leading GPUs and SOCs. This role offers the chance to make a significant impact within a dynamic, technology-driven company, influencing product lines from consumer graphics to self-driving cars and the rapidly expanding field of artificial intelligence.

NVIDIA is renowned for its passionate teams pushing the boundaries of possibility in parallel and visual computing. Our mission is to redefine the future of computing by transforming how graphics are utilized to solve complex challenges in computer science. From simulating imaginative virtual worlds to powering the AI revolution with deep learning algorithms, NVIDIA is at the forefront of innovation.

Take ownership of the verification process for ASIC designs, architectures, golden models, and micro-architectures of PCIE controllers at the IP and sub-system levels. Employ state-of-the-art verification methodologies like UVM to ensure design integrity.

Develop reusable bus functional models, monitors, checkers, and scoreboards, adhering to a coverage-driven verification methodology. This involves a deep understanding of design specifications and implementation to define verification scope, create test plans, tests, and the necessary verification infrastructure.

A B.Tech./M.Tech or equivalent experience is required, along with a minimum of 2 years of relevant experience in verification at the Unit, Sub-system, or SOC level. Expertise in Verilog and SystemVerilog is essential, along with a proven track record in comprehensive verification of IP or interconnect protocols such as PCI Express and USB.

Candidates should demonstrate experience in developing and working within functional coverage-based constrained random verification environments. Familiarity with DV methodologies like UVM/VMM and exposure to industry-standard simulation and debug tools are also crucial. Standing out opportunities include excellent knowledge of PCIE protocol (Gen3 and above), a good understanding of PCIE/CXL system-level architecture, and proficiency in scripting languages like Perl or Python.