Join Google Cloud and shape the future of AI/ML hardware acceleration by driving TPU (Tensor Processing Unit) technology. You will innovate custom silicon solutions that power Google's most demanding AI/ML applications and contribute to products used by millions worldwide. Leverage your design and verification expertise to validate complex digital designs, focusing on TPU architecture and its integration within AI/ML systems.

This role involves developing ASICs to enhance data center traffic efficiency. You will collaborate with architecture, verification, power, and performance teams to deliver high-quality designs for next-generation accelerators. The AI and Infrastructure team is redefining possibilities, empowering Google customers with AI and Infrastructure at unparalleled scale, efficiency, and reliability.

We are at the forefront of groundbreaking innovations, driving the development of AI models, delivering immense computing power, and providing essential platforms for future development. Our teams are shaping hyperscale computing, working on TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, and systems research.

Lead the development of intricate IPs and subsystems alongside a team of engineers.

Take ownership of the microarchitecture and implementation of IPs and subsystems.

Collaborate with Architecture, Firmware, and Software teams to drive feature completion and define microarchitecture specifications.

Champion design methodologies, libraries, debugging, and code reviews in partnership with other IP Design Verification (DV) and Physical Design teams.

Identify and implement Power, Performance, and Area (PPA) improvements for your designated domains.

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline, or equivalent practical experience, is required.

Possess at least 10 years of experience in ASIC development utilizing Verilog/SystemVerilog and VHDL.

Demonstrate experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT).

Exhibit expertise in the micro-architecture and design of IPs and subsystems within the networking domain, including areas like packet processing, bandwidth management, and congestion control.