Shape the future of AI/ML hardware acceleration by driving TPU technology that powers Google's most demanding AI/ML applications. This role offers the opportunity to develop custom silicon solutions and verify complex digital designs with a focus on TPU architecture and its integration within AI/ML-driven systems.

Join a team focused on developing ASICs for data center traffic efficiency. Collaborate across architecture, verification, power, and performance teams to deliver high-quality designs for next-generation data center accelerators. You will tackle complex technical challenges with innovative micro-architecture and practical logic solutions, evaluating design options with performance, power, and area considerations.

Lead the development of intricate IPs and subsystems within the Bengaluru design organization. Take ownership of the microarchitecture and implementation of IPs and subsystems.

Collaborate with Architecture, Firmware, and Software teams to drive feature closure and define microarchitecture specifications. Guide design methodology, libraries, debug, and code reviews in conjunction with other IP Design Verification (DV) and Physical Design teams. Identify and champion Power, Performance, and Area (PPA) improvements for your designated domains.

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience is required. Candidates must possess a minimum of 10 years of experience in ASIC development using Verilog/SystemVerilog and VHDL. Expertise in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT) is essential.

Significant experience in micro-architecture and design of IPs and subsystems within the networking domain, including areas like packet processing, bandwidth management, and congestion control, is also a key requirement.