Shape the future of AI/ML hardware acceleration by driving TPU technology that powers Google's most demanding applications. Join a pioneering team developing custom silicon solutions for Google's TPUs, contributing to innovations behind globally recognized products. Leverage your expertise in design and verification to ensure the integrity of complex digital designs, with a strategic focus on TPU architecture and its integration within AI/ML systems.

This role is central to developing ASICs that enhance traffic efficiency in data centers. You will collaborate closely with architecture, verification, power, performance, and physical design teams to deliver high-quality designs for next-generation data center accelerators. Your mission will involve solving intricate technical challenges with innovative micro-architectural and practical logic solutions, rigorously evaluating design options based on complexity, performance, power, and area.

The AI and Infrastructure team is at the forefront of redefining technological possibilities. We empower Google customers with groundbreaking capabilities and insights through unparalleled scale, efficiency, reliability, and velocity in AI and Infrastructure delivery. Our impact extends to Googlers, Google Cloud customers, and billions of users worldwide.

We are the engine behind Google's transformative innovations, fueling AI model development, providing immense computing power for global services, and offering the foundational platforms for developers building the future. Our teams are actively shaping world-leading hyperscale computing, from software to hardware, focusing on key areas like TPU development, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, and systems research.

Lead the development of complex Intellectual Property (IP) blocks and subsystems alongside a talented team of engineers in the Bengaluru design organization.

Take ownership of the microarchitecture and implementation of key IPs and subsystems.

Collaborate effectively with Architecture, Firmware, and Software teams to finalize features and develop detailed microarchitecture specifications.

Drive advancements in design methodologies, library integration, debugging techniques, and code review processes in close coordination with other IP Design Verification (DV) and Physical Design teams.

Proactively identify and champion Power, Performance, and Area (PPA) optimizations within your assigned domains.

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, complemented by equivalent practical experience, is essential.

Possess a minimum of 10 years of experience in ASIC development, with strong proficiency in Verilog/SystemVerilog and VHDL.

Demonstrate extensive experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT).

Showcase significant experience in the micro-architecture and design of IPs and subsystems within the networking domain, including areas such as packet processing, bandwidth management, and congestion control.