Join NVIDIA, a leader in GPU innovation, as a Memory Mask Design Engineer. You'll be part of a dynamic team pushing the boundaries of high-speed digital memory circuit designs. Contribute to cutting-edge technology and amplify human creativity and intelligence. This role offers an immersive and supportive environment where you can make a significant impact.

Implement IC layouts for high-performance CMOS circuits in advanced process nodes (3nm, 5nm, 7nm and below) using industry-standard methodologies. Deliver custom layouts for digital memory circuits, specializing in IP layout with significant digital components. Implement and refine best layout practices and methodologies for digital memory layouts, adhering to company procedures for IC layout activities.

A Bachelor's or Master's degree in Electronics or a related field is required, coupled with 2+ years of proven experience in Memory layout within advanced CMOS processes. Proficiency in industry-standard EDA tools like Cadence is essential. You should have experience with high-performance memory layouts, a strong understanding of layout basics including bitcells, decoders, and LIO, as well as floor planning and macro-level assembly. Detailed knowledge of top-level verification, EM/IR checks, and layout-dependent effects is also necessary.