Join NVIDIA, a leader in AI computing, as a Verification Engineer focusing on next-generation GPU cores. This role offers a unique opportunity to impact product lines from consumer graphics to AI and autonomous systems. Our global team is dedicated to pushing technological boundaries and shaping the future of computing, driven by a passion for parallel and visual processing.

NVIDIA's GPUs have evolved from rendering virtual worlds to powering complex AI algorithms. We are at the forefront of simulating human intelligence, making our GPUs the brains behind advanced robots and self-driving cars. As an "AI computing company," NVIDIA is transforming how computing solves critical challenges.

As an integral part of our ASIC Verification team, you will contribute to the verification of cutting-edge graphics and compute features within an IP.

Key responsibilities include IP-level verification of GPU ASICs, encompassing design, architecture, golden models, and micro-architecture. You will leverage advanced verification tools and methodologies, working closely with specifications to develop comprehensive test plans, tests, and verification infrastructure utilizing UVM. Ensuring functional and code coverage for all verified RTL is paramount.

Collaboration is key; you will work with HW architects and designers to ensure optimal implementation choices and partner with other verification team members to achieve project goals.

We are seeking candidates with a B.Tech./M.Tech. degree and at least 2 years of relevant experience.

Essential technical skills include strong familiarity with Verilog, C++, and Object-Oriented Programming (OOPs) concepts. Experience in unit-level verification and test planning is required, alongside proficiency in developing and operating within functional coverage-based constrained random verification environments. A solid understanding of computer architecture concepts is crucial.

Demonstrated strong technical fundamentals, superior analytical abilities, and effective problem-solving skills are highly valued. While not mandatory, knowledge of SystemVerilog or similar High-Level Verification Languages (HVLs), coupled with experience in methodologies like UVM/VMM, is a significant advantage. Exposure to industry-standard verification tools for simulation and debugging is also beneficial.