Lead a dynamic team responsible for the end-to-end design and verification of complex hardware IP blocks for NVIDIA’s cutting-edge SmartNIC and DPU products. This pivotal role involves guiding a cluster of IP teams, ensuring the successful delivery of IPs from initial micro-architecture to RTL implementation, functional verification, and silicon readiness. You will foster a high-performing environment, drive parallel project execution, and collaborate closely with architecture, SoC integration, physical design, software, and program management teams to achieve world-class silicon outcomes.

NVIDIA offers a supportive ecosystem with competitive compensation, comprehensive health and wellness programs, financial benefits, generous time off, family support, and extensive learning opportunities. We are committed to fostering an inclusive workplace and providing reasonable accommodations for individuals with disabilities throughout the application and interview process.

Your responsibilities will include leading and mentoring design and verification engineers, defining team structures, and establishing hiring and career development plans. You will oversee the complete IP delivery lifecycle, including micro-architecture, RTL design, functional verification, coverage closure, assertions, formal verification, and synthesis handoff. Setting quality benchmarks, reviewing schedules, and ensuring milestone adherence are key. This role also entails defining and driving verification strategies, test plans, coverage goals, and sign-off criteria, developing UVM-based test environments, and achieving coverage targets. Close collaboration with architecture, SoC integration, physical design, DFT, firmware, and software teams is essential to resolve dependencies, define interfaces, and manage risks. You will also be instrumental in establishing and enhancing design and verification methodologies, best practices, reuse strategies, and automation flows to boost team productivity and IP quality.

We are seeking candidates with a B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, or a related field, complemented by over 10 years of experience in ASIC/SoC design or verification, including at least 2 years in a people management or technical leadership capacity. A strong grasp of digital design fundamentals, including RTL coding (Verilog/SystemVerilog), micro-architecture, timing, clocking, reset, power management, and synthesis constraints, is vital. Proficiency in verification methodologies such as UVM, constrained-random verification, coverage-driven verification, assertions (SVA), and formal verification techniques is required. Experience managing IP delivery across its full lifecycle—from specification to post-silicon support—is essential. The ability to manage multiple IPs or projects concurrently, balancing resources, schedules, and quality trade-offs, is crucial. Familiarity with EDA tools for simulation, linting, CDC, RDC, synthesis, and debug, along with clear communication of technical status, risks, and trade-offs to leadership and cross-functional partners, is expected.