Join NVIDIA, a leader in transforming computer graphics, PC gaming, and accelerated computing, as we pioneer the AI-driven future. Our Silicon Co-Design Group is seeking a skilled High-Speed IO (HSIO) Validation Engineer. This role is pivotal in ensuring the quality and performance of our cutting-edge GPUs, SoCs, and CPUs, powering datacenters, AI, and client markets. You will be at the forefront of silicon validation, working with technologies like PCIe, NVLink, UCIe, USB, and Ethernet to guarantee exceptional performance.

This is an opportunity to shape the next generation of computing hardware. Your expertise will directly influence link margins, BER, and power efficiency, ensuring our products meet the highest standards before they reach our customers. Become a key contributor to NVIDIA's ongoing innovation and technological advancements.

As an HSIO Validation Engineer, you will own the end-to-end characterization and validation of high-speed IO interfaces across silicon, package, and board. This includes developing and executing comprehensive test plans for silicon and SoC-level features, driving power characterization and optimization, and performing systematic root-cause analysis for complex bugs. You will also assess manufacturing implications of IO margin distributions and contribute to the continuous improvement of validation methodologies and automation frameworks.

Key responsibilities include: - Characterizing and validating PCIe, NVLink, UCIe, USB, and Ethernet interfaces. - Developing and executing test plans for silicon bring-up, qualification, and stress testing. - Driving power characterization and optimization across IO interconnects. - Conducting root-cause analysis for HSIO bugs across silicon, package, board, and firmware. - Assessing manufacturing and yield implications of IO margin distributions. - Improving validation methodologies, automation frameworks, and margin-tracking infrastructure.

We are looking for candidates with a Bachelor's or Master's degree in Electrical or Computer Engineering, or a related field, coupled with at least 3 years of experience in post-silicon HSIO validation or characterization. A deep understanding of high-speed serial link protocols such as PCIe Gen5+ and NVLink, alongside SERDES architecture, equalization, and link training, is essential. Strong knowledge of signal integrity and power integrity fundamentals, including S-parameters, eye diagrams, and jitter decomposition, is also required.

Essential qualifications include: - BS or MS in Electrical or Computer Engineering (or equivalent). - 3+ years in post-silicon HSIO validation or characterization. - Deep understanding of high-speed serial link protocols (e.g., PCIe Gen5+, NVLink) and SERDES architecture. - Strong signal integrity and power integrity fundamentals. - Hands-on experience with lab instrumentation (DSOs, BERTs, VNAs, protocol/logic analyzers, TDR). - Proficiency in DOE, shmoo/margin-trending, and Python-based test automation. - Proven ability to drive cross-functional debug across chip, package, board, firmware, driver, and system teams.