Join NVIDIA, a pioneer in graphics, gaming, and accelerated computing, as we define the future of AI. Our GPUs are the brains behind intelligent systems, powering computers, robots, and autonomous vehicles. We are seeking a highly skilled High Speed IO Validation Engineer to characterize and qualify essential high-speed interfaces. This role is crucial for bringing new silicon from initial power-on to large-scale production, ensuring seamless performance across datacenters, AI, and client markets. You will be at the forefront of innovation, working with cutting-edge technologies like PCIe, NVLink, and UCIe.

As an HSIO Validation Engineer, you will spearhead the end-to-end characterization and validation of high-speed I/O interfaces, including PCIe, NVLink, NVLink-C2C, UCIe, USB, UFS, and Ethernet. Your responsibilities will span across silicon die, package, and board on NVIDIA GPUs, CPUs, and SoCs.

You will develop and execute comprehensive validation test plans covering silicon and SoC-level HSIO features. This includes bring-up, corner qualification, stress testing, productization, and structured Design of Experiments (DOE) across various PVT, board, cable/connector, thermal, and firmware variables. A key focus will be left-shifting silicon failures before deployment.

Furthermore, you will drive power characterization and optimization for IO interconnects using workload-representative stimuli. Analyzing trade-offs across V/F, lane configuration, and protocol states will be essential for feeding back insights into design, firmware, and binning processes. You will also conduct systematic root-cause analysis for complex HSIO bugs, collaborating with cross-functional teams to ensure upstream fixes.

Candidates should possess a Bachelor's or Master's degree in Electrical or Computer Engineering, or a related field, with a minimum of 8 years of experience in post-silicon HSIO validation or characterization. A deep understanding of high-speed serial link protocols such as PCIe Gen5+, NVLink, NVLink-C2C, UCIe, and CXL is required, along with expertise in SERDES architecture, equalization, link training, and electrical characterization.

Strong fundamentals in Signal Integrity (SI) and Power Integrity (PI), including S-parameters, eye diagrams, channel margin, crosstalk, return loss, PDN noise, and jitter decomposition, are essential. You should have hands-on experience with lab instrumentation like DSOs, BERTs, VNAs, protocol/logic analyzers, and TDRs. Proficiency in DOE/shmoo/margin-trending methodologies and Python-based test automation is also a must.

Experience with PCIe Gen5/Gen6 or NVLink validation on production silicon, including link training, equalization tuning, BER margining, or compliance debug, will set you apart. Prior SERDES, mixed-signal, or analog circuit design experience is advantageous. The ability to translate rack-environment conditions into silicon/board characterization and comfort using AI productivity tools for workflow optimization are highly desired.