Join our team as a Functional Verification Engineer and play a key role in ensuring the functional correctness of digital designs. You will develop and implement advanced testbenches, create sophisticated test scenarios using SystemVerilog and UVM, and collaborate closely with design and architecture teams. Your expertise will be crucial in identifying edge cases and guaranteeing complete functional coverage before tape-out, contributing to high-quality hardware development.

As a Functional Verification Engineer, you will independently drive verification tasks and become a subject matter expert. Active participation in team discussions and contributing solutions to complex problems are expected. You'll collaborate with design and architecture teams to refine verification processes, meticulously document verification plans, test cases, and results, and mentor junior team members. Continuous improvement of verification environments and methodologies to boost efficiency and coverage is also a key aspect of this role.

This role requires a minimum of 2 to 5 years of experience in Functional Verification, with a strong focus on SoC Verification. Proficiency in SystemVerilog and the Universal Verification Methodology (UVM) is essential for creating robust testbenches and test cases. A solid understanding of constrained-random and coverage-driven verification techniques is necessary, along with the ability to develop directed tests and analyze simulation results effectively. Familiarity with digital design concepts and hardware description languages, coupled with strong collaboration skills, is vital for ensuring comprehensive verification coverage. A 15-year full-time education is also a prerequisite.