Join our team as a Functional Verification Engineer and play a crucial role in ensuring the functional correctness of complex digital designs. You will be instrumental in developing and executing advanced testbenches at both block and system levels.

This role involves creating sophisticated test scenarios, including constrained-random, directed, and coverage-driven tests, utilizing languages like SystemVerilog and UVM. Close collaboration with design and architecture teams is essential to pinpoint critical corner cases and achieve comprehensive functional coverage before product tape-out.

As an integral team member, you are expected to work independently and develop subject matter expertise. Active contribution to team discussions and problem-solving is vital. You will assist in documenting verification plans and results to support design reviews, and mentor junior engineers by sharing knowledge.

Continuous learning to stay abreast of the latest verification techniques and tools is encouraged. Effective collaboration with cross-functional teams will ensure alignment on project objectives and timelines, contributing to overall project success.

This position requires a minimum of 3 years of dedicated experience in SoC Verification. A strong command of SystemVerilog and the Universal Verification Methodology (UVM) for testbench development is mandatory. You should possess a deep understanding of verification methodologies like constrained-random and coverage-driven testing.

Furthermore, the ability to analyze complex digital designs, identify potential corner cases, and effectively debug simulation issues is crucial. Experience working with design and architecture teams to improve verification coverage and quality is also a key requirement. A 15-year full-time education is a prerequisite for this role.