Join our Silicon Engineering team as a Functional Verification Engineer, contributing to cutting-edge digital design validation. You will develop and execute advanced testbenches to ensure the functional correctness of designs at block and system levels. This role involves creating sophisticated test scenarios, including constrained-random and coverage-driven approaches, to thoroughly test designs before tape-out.

This position emphasizes collaboration with design and architecture teams to identify complex edge cases and guarantee comprehensive functional coverage. A proactive approach to problem-solving and clear communication are key to achieving high-quality verification outcomes and driving innovation.

Independently take ownership and become a subject matter expert in functional verification. Actively participate and contribute to team discussions, offering solutions to work-related challenges. Develop and maintain robust verification environments to support design validation efforts. Analyze verification results meticulously and debug issues to enhance test coverage and overall quality.

Provide valuable support to junior team members by sharing expertise and assisting in their professional development. Ensure timely and effective execution of verification tasks, contributing to project success and team growth.

A minimum of 3 years of experience in SoC Verification is essential for this role. Proficiency in SystemVerilog and Universal Verification Methodology (UVM) is required. Strong understanding of digital design principles and hardware description languages is crucial. Experience in developing constrained-random and directed test scenarios to achieve comprehensive coverage is necessary.

Familiarity with coverage-driven verification techniques and relevant tools is important. The candidate must possess strong debugging skills and the ability to analyze simulation results effectively to identify and resolve design issues. A solid foundation in 15 years of full-time education is a prerequisite.