Join NVIDIA, a company at the forefront of innovation, as a DFT Engineer. We pioneered the GPU, transforming PC gaming, graphics, and parallel computing. As AI research accelerates, the demand for scalable computation is unprecedented, and NVIDIA GPUs are leading the way. Embrace this opportunity to contribute to groundbreaking semiconductor chip design within our Design-for-Test Engineering team.

This role involves developing creative solutions for DFT architecture, verification, and post-silicon validation on some of the industry's most complex chips. We are seeking a dedicated DFT Engineer to join our pioneering efforts.

As a key member of our team, you will manage the entire DFT lifecycle, from RTL design and gate-level scan insertion to comprehensive verification, including JTAG, boundary scan, security protocols, and test clocking across diverse ATPG configurations. You'll also be instrumental in the verification and silicon bring-up of Scan ATPG and other DFT features.

Your role extends to developing and implementing advanced DFT methodologies for next-generation products. We encourage you to contribute to innovation and continuously improve DFT quality. Collaboration with cross-functional teams to integrate DFT features seamlessly into chip designs is also a core part of this position.

Candidates should possess a BSEE or MSEE from reputable institutions, or equivalent experience with a minimum of 2 years in the field. A strong understanding of static timing analysis, ECO, ASIC/Logic Design flow, HDL, and digital logic design is essential.

Experience in RTL and gate-level verification and simulation is required. Familiarity with BIST architecture and JTAG/IEEE1149.1/IEEE1500 standards is necessary. Proficiency in Scan ATPG, compression techniques, and memory testing is a must. Excellent analytical and problem-solving skills, coupled with strong scripting abilities in Perl or Python, are also highly valued.