Join Capgemini Engineering, a global leader in engineering services, and contribute to innovative R&D and engineering solutions. We empower the world's most forward-thinking companies, from autonomous vehicles to advanced robotics, by leveraging cutting-edge digital and software technologies. This is your opportunity to join a dynamic team where you can make a significant impact, experience diverse challenges daily, and build a career filled with growth possibilities.

Define the architecture and strategy for SoC DFT at both subsystem and top levels. Establish robust ATPG, Scan, MBIST, and LBIST approaches. Drive test coverage goals and ensure all DFT quality benchmarks are met. Develop and implement efficient test compression and diagnosis methods. Collaborate closely with RTL, Verification, and Physical Design teams to ensure seamless DFT implementation and integration. Oversee DFT sign-off requirements and liaise with customer test and manufacturing groups for all DFT-related needs. Provide comprehensive DFT support from initial architecture phases through to SoC tapeout.

A minimum of 12 years of specialized experience in DFT is required, with a proven track record of multiple successful SoC tapeouts. Deep expertise in RISC and ARM SoC DFT strategies for both subsystems and top-level designs is essential. Hands-on proficiency in Scan Insertion and ATPG, coupled with a strong understanding of MBIST and LBIST, is critical. Practical experience with Tessent and/or Synopsys DFT tools is necessary. Solid knowledge of test compression, diagnosis methodologies, JTAG, IEEE 1500, and IEEE 1687 is expected. While not mandatory, experience in Safety DFT, automotive test methodologies, silicon bring-up, yield learning, diagnosis, chiplet test architecture, and advanced-node test challenges will be advantageous. Exceptional analytical, problem-solving, collaborative, and communication skills are fundamental.