As a Design Verification Solution Architect, you will spearhead the verification strategy for sophisticated SoCs and subsystems. Your role is pivotal in ensuring complete verification closure from initial specification through to tapeout, employing scalable and advanced methodologies.

This position offers the chance to define comprehensive SoC/IP verification architectures and strategies. You will establish the verification plan, define coverage models, and guide the development of UVM-based verification environments.

You will lead critical aspects of subsystem and full-chip verification, driving initiatives in low-power, performance, emulation, and FPGA verification. Conducting verification reviews with customers and supporting methodology standardization and automation are key responsibilities.

• Define and lead the verification strategy for complex SoCs and subsystems. • Establish the verification plan and coverage model. • Guide UVM-based verification environments. • Lead subsystem and full-chip verification efforts. • Drive low-power, performance, emulation, and FPGA verification. • Conduct thorough verification reviews with customers. • Support methodology standardization and automation initiatives.

A minimum of 12 years of experience in verification is required, with a proven track record of leading multiple SoC verification programs to successful tapeout. Expertise in UVM, SystemVerilog, and Assertions is essential.

Candidates must possess experience in SoC boot verification using boot code and demonstrate strong coverage-driven verification expertise. Familiarity with ARM/RISC-V based compute subsystems, security subsystems, NoC, and debug is necessary.

Experience with emulation-based acceleration platforms like Palladium, Zebu, or Veloce is required. Additionally, knowledge of high-speed protocols such as PCIe, DDR, Ethernet, and UCIe is expected, along with an understanding of AI-assisted verification flows.