Join a pioneering team dedicated to crafting custom silicon solutions that propel Google's direct-to-consumer products into the future. Your contributions will drive innovation behind beloved products enjoyed by millions globally. You will play a key role in shaping next-generation hardware, delivering exceptional performance, efficiency, and seamless integration.

Google is committed to organizing the world's information and making it universally accessible and useful. Our team synergizes Google AI, Software, and Hardware expertise to engineer groundbreaking, helpful experiences. We actively research, design, and develop advanced technologies and hardware to enhance computing speed, fluidity, and power, ultimately aiming to improve lives through technology.

Lead and manage comprehensive verification activities for complex System-on-Chip (SoC) architectures, ensuring robust quality standards from pre-silicon to tape-out. Manage and mentor high-performing engineering teams, driving execution, fostering a culture of technical excellence, and supporting career growth.

Drive SoC-level pre-silicon emulation strategies (e.g., Palladium, Zebu, SimXL) to accelerate hardware-software co-verification, boot operating systems, and catch complex system-level bugs early. Oversee complex post-silicon debug activities, collaborating closely with post-silicon validation teams to root-cause silicon issues, bring up hardware, and correlate pre-silicon verification coverage with actual silicon behavior.

Develop and scale aspects of logic verification infrastructure and advanced methodologies across the SoC, maintaining strong integration standards with architecture, design, and cross-functional teams.

A Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience is required, alongside a minimum of 15 years in front-end design or design verification. Essential experience includes power-aware verification methodologies and familiarity with fabric and interconnect architectures and cache coherency protocols.

Preferred qualifications include a Master's degree in Electrical Engineering or Computer Science. Expertise in verifying high-bandwidth memory subsystems (DDR5, LPDDR5, HBM), including physical layer (PHY) training, memory controllers, and JEDEC compliance, is highly desirable. Significant experience leading engineering teams to successfully deliver complex SoCs is crucial, as is technical mastery in SoC-level verification and UVM-based environments. Experience with pre-silicon emulation platforms and hardware accelerators is also a plus.