Join a pioneering team dedicated to developing advanced custom silicon solutions that will define the future of Google's direct-to-consumer products. Your contributions will be instrumental in driving innovation for products used by millions globally, shaping next-generation hardware experiences with superior performance, efficiency, and seamless integration.

Google is committed to organizing the world's information and making it universally accessible and useful. Our division merges Google's leading AI, Software, and Hardware expertise to create groundbreaking, helpful experiences. We are at the forefront of researching, designing, and developing cutting-edge technologies and hardware to achieve faster, more powerful, and seamless computing, ultimately aiming to enhance lives through technology.

Lead and manage comprehensive verification efforts for intricate System-on-Chip (SoC) architectures, ensuring stringent quality from pre-silicon through tape-out.

Direct and mentor high-caliber engineering teams, driving project execution, cultivating technical excellence, and supporting professional development.

Spearhead SoC-level pre-silicon emulation strategies, utilizing platforms like Palladium, Zebu, and SimXL to expedite hardware-software co-verification, OS boot processes, and early detection of complex system-level defects.

Oversee sophisticated post-silicon debug activities, collaborating closely with validation teams to resolve silicon issues, facilitate hardware bring-up, and reconcile pre-silicon coverage with actual silicon performance.

Develop and scale logic verification infrastructure and advanced methodologies across the SoC, maintaining robust integration standards with architecture, design, and cross-functional teams.

A Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience is required.

Fifteen years of experience in front-end design or design verification is essential.

Proficiency in power-aware verification methodologies is necessary.

Experience with fabric and interconnect architectures, along with cache coherency protocols, is expected.

Preferred qualifications include a Master's degree in Electrical Engineering or Computer Science, or equivalent practical experience.

Experience verifying high-bandwidth memory subsystems (DDR5, LPDDR5, HBM), including PHY training, memory controllers, and JEDEC compliance, is beneficial.

Extensive experience in direct management of high-performing engineering teams with a proven history of delivering complex, production-grade SoCs is highly valued.

Strong technical expertise in SoC-level verification and fundamental design verification (DV) principles using UVM-based environments is crucial. Direct experience with pre-silicon emulation platforms and hardware accelerators (e.g., SimXL, formal verification, or portable stimulus standard/PSS) is a significant advantage.

Excellent programming skills in SystemVerilog, Verilog, and scripting languages such as Python or Perl are required.