Join a pioneering team at Google Cloud, shaping the future of custom silicon solutions that power Google's direct-to-consumer products. You will be instrumental in driving innovation for hardware experiences, focusing on unparalleled performance, efficiency, and integration for millions of users worldwide.

Our AI and Infrastructure team is at the forefront of redefining possibilities, enabling Google customers with groundbreaking capabilities and insights. We deliver AI and Infrastructure at unmatched scale, efficiency, reliability, and velocity, serving Googlers, Google Cloud customers, and billions of users globally. As a key player, you will be a driving force behind Google's innovations, empowering cutting-edge AI models and delivering exceptional computing power.

You will be responsible for the complete verification life-cycle, from meticulous planning and test execution to achieving coverage closure. A key focus will be meeting rigorous AI/ML performance and accuracy goals. This includes building sophisticated constrained-random verification environments designed to uncover corner-case bugs, thereby ensuring the utmost reliability of Artificial Intelligence/Machine Learning workloads on Tensor Processing Unit (TPU) hardware. Close collaboration with design and verification engineers on active projects is essential.

Responsibilities include: - Planning digital design block verification by thoroughly understanding specifications and collaborating with design engineers on key scenarios. - Leading chip engineering teams, task planning, resource allocation, and conducting design/code reviews. - Developing critical verification features and capabilities. - Making technical decisions and providing project status updates in conjunction with system, software, design, and physical implementation stakeholders. - Spearheading design verification efforts and fostering collaboration with both internal and external partners.

This role requires a minimum of 10 years of experience in hardware verification languages such as System Verilog or Specman, coupled with a deep understanding of design verification methodologies and the chip design flow. A proven ability to create detailed chip or subsystem design verification strategies and plans is crucial. Candidates must demonstrate experience leading design verification teams through the entire development cycle, from initial concept to final delivery.

Preferred qualifications include a Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with a specialization in computer architecture. Experience verifying digital systems with standard IP components like microprocessor cores and hierarchical memory subsystems is highly valued. Familiarity with verification techniques, the full verification life cycle, performance verification of ASICs, and ASIC standard interfaces are also considered advantageous. Experience across multiple SOC projects and cycles in at least three products is a significant plus.