Join a pioneering team at Google Cloud, driving innovation in custom silicon solutions that power Google's direct-to-consumer products. You will play a crucial role in shaping the future of hardware, delivering exceptional performance, efficiency, and integration for products used by millions globally. Your contributions will define the next generation of user experiences.

This role is integral to the AI and Infrastructure team, which is redefining possibilities by delivering AI and Infrastructure at unprecedented scale, efficiency, and reliability. Our solutions empower Google customers, Googlers, and billions of users worldwide with breakthrough capabilities and insights.

You will lead the entire verification life-cycle, from meticulous planning and rigorous test execution to ensuring complete coverage closure, with a strong focus on meeting stringent AI/ML performance and accuracy targets. Develop advanced constrained-random verification environments designed to uncover critical corner-case bugs and guarantee the robustness of AI/ML workloads on Tensor Processing Unit (TPU) hardware. Foster close collaboration with design and verification engineers on active projects and conduct thorough verification processes.

Key responsibilities include: - Planning the verification of digital design blocks by thoroughly understanding specifications and collaborating with design engineers to identify critical verification scenarios. - Leading and mentoring a team of chip engineers, including task planning, resource allocation, and conducting design/code reviews. - Developing critical verification features and capabilities. - Making key technical decisions and representing project status by working closely with system, software, design, and physical implementation stakeholders. - Spearheading design verification efforts and engaging with external and internal partners.

Candidates should possess a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline, or equivalent practical experience. A minimum of 10 years of hands-on experience is required in hardware verification languages such as System Verilog/Specman, design verification methodologies, and the chip design flow. Proven experience in creating detailed chip or subsystem design verification strategies and comprehensive plans is essential.

Additionally, candidates must demonstrate extensive experience in leading design verification teams through the complete development cycle, from initial concept to final delivery. Preferred qualifications include a Master's degree or PhD in a relevant engineering or computer science field with a focus on computer architecture. Experience with verifying digital systems using standard IP components, advanced verification techniques, performance verification of ASICs, and ASIC standard interfaces is highly advantageous.