Contribute to shaping the future of AI/ML hardware acceleration by driving TPU technology for Google's demanding AI/ML applications. This role involves developing custom silicon solutions, pushing boundaries in hardware development, and leveraging expertise in design and verification for complex digital designs, with a focus on TPU architecture and its integration within AI/ML systems. You'll be part of an innovative team that powers Google's groundbreaking advancements, delivering unparalleled computing power and essential platforms for developers.

The AI and Infrastructure team is redefining possibilities, empowering customers with breakthrough AI and Infrastructure capabilities at unmatched scale and efficiency. We serve Googlers, Google Cloud customers, and billions of users worldwide. Our work is fundamental to Google's AI models, global services, and the development of world-leading hyperscale computing, including TPUs, Vertex AI, Google Global Networking, and data center operations.

Own the complete verification life cycle, from planning and test execution to coverage closure, ensuring stringent AI/ML performance and accuracy goals are met. Develop constrained-random verification environments capable of identifying corner-case bugs and guaranteeing the reliability of AI/ML workloads on TPU hardware. Collaborate closely with design and verification engineers on active projects, actively participating in verification tasks.

Key responsibilities include: - Planning verification for digital design blocks and engaging with design engineers to define critical verification scenarios. - Identifying and implementing diverse coverage measures for stimulus and corner-cases. - Debugging tests in conjunction with design engineers to ensure functionally correct design blocks. - Measuring progress towards tape-out by identifying verification gaps and demonstrating advancements. - Creating constrained-random verification environments utilizing SystemVerilog and UVM.

A Bachelor's degree in Electrical Engineering or equivalent practical experience is required, coupled with 4 years of experience in verification. This includes verifying digital logic at the RTL level using SystemVerilog or Specman/E for FPGAs or ASICs. Experience is also needed in verifying digital systems with standard IP components/interconnects, such as microprocessor cores and hierarchical memory subsystems.

Candidates should possess experience in the verification and debugging of IP/subsystem/SoCs within the networking domain, specifically focusing on packet processing, bandwidth management, and congestion control. A Master's degree in Electrical Engineering or a related field, alongside experience with industry-standard simulators, revision control systems, regression systems, and AI/ML accelerators or vector processing units, is preferred. Familiarity with the full verification life cycle and excellent problem-solving and communication skills are also advantageous.