Join an innovative team pushing the boundaries of custom silicon solutions that will power the future of Google's direct-to-consumer products. You will be instrumental in developing next-generation hardware experiences, focusing on unparalleled performance, efficiency, and integration. Your expertise will directly contribute to products enjoyed by millions globally, shaping the next wave of hardware innovation.

As part of the Silicon team, you will verify advanced custom silicon accelerators and SoCs. This role involves building sophisticated Universal Verification Methodology (UVM) test environments and close collaboration with design, architecture, and emulation teams to ensure the delivery of production-quality silicon. This position is within the Platforms and Devices area, which focuses on Google's diverse computing software platforms and first-party devices, integrating AI, software, and hardware to create seamless and faster user interactions.

Develop and refine constrained-random verification environments utilizing SystemVerilog and UVM. Employ SystemVerilog Assertions (SVA) and formal tools for comprehensive formal verification.

Conduct power-aware simulations and formal verification to validate power management features, including clock gating, power gating, and Dynamic Voltage and Frequency Scaling (DVFS). Develop and implement robust power-aware test cases, covering stress and corner-case scenarios for optimal power integrity.

Create and execute coverage-driven verification plans to guarantee thorough coverage of ASIC designs. Partner with design engineers to address coverage gaps and enhance overall design quality.

Plan the verification strategy for complex digital design blocks by thoroughly understanding design specifications and collaborating with design engineers to identify critical verification scenarios.

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience is required.

Four years of hands-on experience verifying digital logic at RTL using System Verilog for both FPGAs and ASICs is essential.

Proven experience with UVM Testbenches and environments is a prerequisite.

Preferred qualifications include a Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with a specialization in computer architecture. Expertise in building and utilizing UVM verification components and environments at the IP or Subsystem level is highly desirable. Experience with image processing, computer vision, or machine learning IPs, along with familiarity with AMBA (APB/AXI/ACE) or other standard protocols, is also beneficial. A strong understanding of CPU, GPU, or other compute/ML architectures, coupled with excellent communication and cross-functional collaboration skills, will set candidates apart.