Shape the future of AI/ML hardware acceleration as a Silicon Architect/Design Engineer. This role drives the development of Tensor Processing Units (TPUs) powering Google's most demanding AI/ML applications.

Collaborate with hardware and software architects to define, design, and model next-generation TPUs. You will be involved in product definition, design implementation, and ensuring an optimal balance of performance, power, features, schedule, and cost.

Revolutionize ML workload characterization and benchmarking, proposing enhancements for future TPUs. Develop architecture specifications aligned with AI/ML roadmap requirements and create power/performance models and RTL designs. Partner with hardware design, software, compiler, ML model, and research teams for effective hardware/software co-design. Drive advanced AI/ML capabilities and implement efficient design verification strategies. Utilize AI techniques for optimal physical design convergence and validate DFT, post-silicon test, and debug strategies.

A PhD degree in Electronics and Communication Engineering, Electrical Engineering, Computer Engineering, or a related technical field, or equivalent practical experience. Proficiency in programming languages such as C++, Python, and Verilog. Experience with industry-standard tools like Synopsys and Cadence. Demonstrated experience with accelerator architectures and data center workloads.

Preferred qualifications include 2 years of silicon domain experience post-PhD, familiarity with performance modeling tools, and knowledge of high-performance, low-power design techniques, arithmetic units, bus architectures, accelerators, or memory hierarchies.