Shape the future of AI/ML hardware acceleration as a Silicon Architect/Design Engineer. Drive TPU technology that powers Google's most demanding AI/ML applications.

Collaborate with hardware and software architects to define, design, and model next-generation TPUs. Responsibilities span product definition, design, and implementation, focusing on balancing performance, power, features, schedule, and cost.

This role is part of the Technical Infrastructure team, building the architecture behind Google's products. We develop and maintain data centers and create next-generation platforms, ensuring optimal user experience through robust networks and infrastructure.

Characterize and benchmark Machine Learning (ML) workloads, proposing optimizations for future TPUs. Develop architecture specifications to meet AI/ML roadmap requirements. Create power/performance models, microarchitecture, and RTL designs, evaluating their impact. Partner with hardware design, software, compiler, and ML model teams for effective hardware/software co-design and high-performance interfaces. Advance AI/ML capabilities and drive efficient design verification strategies. Utilize AI techniques for optimal physical design convergence and investigate/optimize DFT, post-silicon test, and debug strategies.

Requires a PhD in Electronics and Communication Engineering, Electrical Engineering, Computer Engineering, or a related technical field, or equivalent practical experience. Proficiency in programming languages such as C++, Python, and Verilog is essential. Experience with industry-standard tools like Synopsys and Cadence is required. Familiarity with accelerator architectures and data center workloads is necessary. Preferred qualifications include 2 years of silicon domain experience post-PhD and knowledge of performance modeling tools.