Shape the future of AI/ML hardware acceleration as a Silicon Architect/Design Engineer. Drive TPU technology powering Google's most demanding AI/ML applications. Collaborate with hardware and software architects and designers to architect, model, analyze, define, and design next-generation TPUs.

Responsibilities are dynamic and multi-faceted, covering product definition, design, and implementation. Partner with engineering teams to achieve the optimal balance between performance, power, features, schedule, and cost.

This role is part of the Technical Infrastructure team, responsible for the architecture that keeps Google's products running. This includes data center development, building next-generation platforms, and ensuring network reliability for an exceptional user experience.

Revolutionize Machine Learning (ML) workload characterization and benchmarking, proposing capabilities and optimizations for next-generation TPUs. Develop architecture specifications aligned with current and future AI/ML roadmap requirements. Create architectural and microarchitectural power/performance models, RTL designs, and evaluate performance and power metrics.

Partner with hardware design, software, compiler, ML model, and research teams for effective hardware/software co-design, establishing high-performance hardware/software interfaces.

Advance and integrate AI/ML capabilities, driving efficient design verification strategies. Utilize AI techniques for faster and optimal physical design convergence, including timing, floor planning, power grid, and clock tree design. Investigate, validate, and optimize DFT, post-silicon test, and debug strategies to enhance silicon bring-up and qualification.

A PhD degree in Electronics and Communication Engineering, Electrical Engineering, Computer Engineering, or a related technical field is required, or equivalent practical experience.

Proficiency in programming languages such as C++, Python, and Verilog is essential. Experience with Synopsys and Cadence tools is necessary.

Demonstrated experience with accelerator architectures and data center workloads is a key requirement. Preferred qualifications include 2 years of Silicon domain experience post-PhD, familiarity with performance modeling tools, and knowledge of arithmetic units, bus architectures, accelerators, memory hierarchies, high performance, and low power design techniques.