Shape the future of AI/ML hardware acceleration by joining our Silicon Architect/Design Engineer team. You will drive TPU technology essential for Google's most demanding AI/ML applications.

Collaborate with leading hardware and software architects to define, model, and design next-generation TPUs. This dynamic role involves product definition, design, and implementation, focusing on optimizing performance, power, features, schedule, and cost.

Join the Technical Infrastructure team, the backbone of Google's online services. We build and maintain data centers and next-generation platforms, ensuring the best and fastest user experience.

Pioneer Machine Learning (ML) workload characterization and benchmarking, proposing optimizations for future TPUs.

Develop architecture specifications aligned with AI/ML roadmaps. Create power/performance models, RTL designs, and conduct thorough performance and power analysis.

Engage with hardware design, software, compiler, ML model, and research teams for effective hardware/software co-design and high-performance interfaces.

Implement advanced AI/ML capabilities and drive efficient design verification strategies.

Utilize AI techniques for accelerated physical design convergence, including timing and floor planning. Investigate and optimize DFT, post-silicon test, and debug strategies for silicon bring-up.

A PhD in Electronics and Communication Engineering, Electrical Engineering, Computer Engineering, or a related technical field, or equivalent practical experience is required.

Proficiency in programming languages like C++, Python, and Verilog is essential, along with experience using Synopsys and Cadence tools.

Demonstrated experience with accelerator architectures and data center workloads is expected.

Preferred qualifications include 2 years of silicon domain experience post-PhD, familiarity with performance modeling tools, and knowledge of arithmetic units, bus architectures, accelerators, memory hierarchies, and high-performance/low-power design techniques.