Join Microsoft's innovative Silicon team, building cutting-edge custom silicon for diverse systems, from Xbox to Azure cloud servers.

We are seeking a motivated Design Verification Engineer for the dynamic Artificial Intelligence Silicon Engineering (AISiE) team. This role is ideal for a self-starter eager to contribute in a fast-paced, technical environment.

Microsoft's mission is to empower every individual and organization globally. We foster a culture of growth, innovation, and collaboration, driven by our core values of respect, integrity, and accountability. We are committed to creating an inclusive environment where everyone can thrive.

As part of the AISiE silicon team, you will contribute to delivering premium-quality, high-performance custom IP and SoC designs.

Your key responsibilities will include: - Planning verification strategies in collaboration with architecture and design engineers. - Developing and enhancing verification environments using SystemVerilog and UVM, or employing formal verification with SVA and leading tools. - Creating tests using UVM or C/C++. - Analyzing and debugging test failures to ensure design correctness. - Identifying and writing functional coverage for stimulus and corner cases. - Achieving coverage closure to meet tape-out requirements.

We are looking for candidates with: - A minimum of 4 years of experience in design verification, with a proven history of delivering complex CPU or SoC IPs. - A strong understanding of verification principles, testbenches, stimulus generation, and UVM or C++ based test environments. - Good knowledge of computer architecture. - Substantial experience in debugging RTL (Verilog) designs, simulation, and/or emulation environments. - Proficiency in scripting languages such as Python or Perl.