Join Microsoft's innovative Silicon team, a driving force behind cutting-edge technology for diverse systems. Our Artificial Intelligence Silicon Engineering (AISiE) team is seeking a highly motivated Design Verification Engineer to contribute to the development of advanced AI silicon.

Embrace a dynamic, high-tech environment where collaboration and a growth mindset are key. We are committed to Microsoft's mission of empowering every person and organization on the planet to achieve more. Our values of respect, integrity, and accountability foster an inclusive culture where everyone can thrive.

As a Design Verification Engineer in the AISiE team, you will be instrumental in delivering premium-quality, high-performance custom IP and SoC designs.

Key responsibilities include: - Planning verification strategies for complex IP/SoC interactions with architecture and design teams. - Developing and enhancing constrained-random verification environments using SystemVerilog and UVM, or performing formal verification with SVA. - Creating tests using UVM or C/C++. - Analyzing and debugging test failures in collaboration with designers to ensure design correctness. - Identifying and implementing functional coverage for stimulus and corner cases. - Achieving full coverage to meet tape-out requirements.

We are looking for a candidate with a minimum of 3 years of experience in design verification, demonstrating a strong track record of delivering complex CPU or SoC IPs.

Essential qualifications include: - Solid understanding of verification principles, testbenches, stimulus generation, and UVM or C++ based test environments. - Good grasp of computer architecture. - Substantial experience in debugging RTL (Verilog) designs and simulation/emulation environments. - Proficiency in scripting languages such as Python or Perl.